1. Field of the Invention
The present invention relates to a semiconductor device and fabricating method thereof, and more particularly, to a capacitor and a fabricating method thereof, by which capacitance is enhanced by increasing an effective area of a lower electrode of the capacitor.
2. Discussion of the Related Art
Generally, in a unit cell configured with a MOS transistor and a capacitor, device characteristics are considerably affected by capacitance of the capacitor. As a capacitor occupying area is reduced according to a highly increasing degree of semiconductor device integration, large capacitance of a capacitor is badly needed more than ever.
To increase capacitance of a capacitor, there are various methods such as a method of increasing an effective area of a capacitor, a method of thinning a dielectric layer between upper and lower electrodes, a method of forming a dielectric layer of a high dielectric constant, and the like.
Yet, the method of thinning a dielectric layer lowers reliability of a semiconductor device. And, the method of forming a dielectric layer of a high dielectric constant needs to develop a new capacitor fabricating process.
Hence, many efforts are made to develop the method of increasing an effective area.
FIG. 1 is a cross-sectional diagram of a capacitor in a semiconductor device according to a related art.
Referring to FIG. 1, a lower electrode 102, a dielectric layer 104, and an upper electrode 105 are sequentially stacked on a semiconductor substrate 101 to configure a capacitor embedded in an insulating interlayer 103.
In such a capacitor structure of the related art, since the lower electrode 102 has a planar shape, an area of the lower electrode 102 is decreased according to a reduced design rule of semiconductor device.
Hence, a structural limitation is put on the related art capacitor in maximizing capacitance in a microscopic device.